1. Field of the Invention
The invention relates to the field of MOS dynamic RAM cells, particularly those compatible with CMOS processing.
2. Prior Art
For the most part, commercial metal-oxide-semiconductor (MOS), random-access memories (RAMs) are fabricated with memory cells consisting of a single transistor and a capacitor. A typical prior art version of this cell is described in U.S. Pat. No. 3,387,286.
The present invention discloses a dynamic RAM cell, compatible with complementary MOS (CMOS) processing which consists of a single transistor and a capacitance means. The cell has several advantages over the prior art, including the fact that it is fabricated with substantially fewer field oxide regions, thus providing higher density.
One advantage to the described cell is its high immunity to alpha particles. In typical n-channel dynamic RAMS, particularly higher density RAMs (e.g. 16K, 64K and 256K), incident alpha particles cause ionization within the substrate. Minority carriers then drift into active regions (storage capacitors and sensing bit line) causing failures. The present cell which is fabricated in an n-type well, has high immunity to these minority carriers because of the barrier produced at the interface between the well and substrate, thus protecting both the signal charge in the storage capacitor and the sensing bit lines.